The present invention relates to a complementary metal oxide semiconductor (CMOS) device and, more particularly, to a serial input/output device including a CMOS shift register.
Recently, CMOS devices are used in microprocessors and microcomputers. Further, a CMOS one-chip microcomputer including a serial input/output processing device has been developed. In such a CMOS device, one of the main objects is to minimize the power consumption. In the conventional CMOS serial input/output data processing system, the power consumption is mainly caused by the data transferring operation conducted in the shift register.
Generally, the current consumption IDD in the CMOS shift register is represented as follows: EQU IDD=f.multidot.CL.multidot.VDD
where f is the operating frequency of the CMOS circuit, CL is the load capacity, and VDD is the power supply voltage. It will be clear from the above equation that the power consumption is theoretically zero when the data transfer clock signal is not applied to the CMOS circuit.
Accordingly, an object of the present invention is to provide a CMOS circuit which minimizes the power consumption.
Another object of the present invention is to minimize the power consumption in a shift register included in a CMOS serial input/output processing device.
Other objects and further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
To achieve the above objects, pursuant to an embodiment of the present invention, a detection circuit is provided for detecting whether a serial transmitting data or a serial receiving data exists in a serial input/output data processing circuit. In response to a detection output of the detection circuit, a data transfer clock is applied to a data transmitting shift register or a data receiving shift register only when the transmitting data or the receiving data exists.